Most Verilog testbenches pass when they shouldn't. Here's the pattern I see constantly in FPGA and ASIC projects — and the fix that takes 30 minutes.

The Problem

initial begin
  a = 8'hFF; b = 8'h01; op = 3'b000;
  #10;
  $display("result = %h", result);
  $finish;
end

Notice what's missing? There's no check. The testbench runs, prints a number, and the engineer eyeballs it. "Looks right." Ship it.

This is how million-dollar respin bugs happen.

The Fix: Self-Checking Architecture

1. Golden model — software implementation of the same function your RTL computes

2. Scoreboard — collects expected and actual results, then compares

3. Automatic pass/fail — the simulation tells you whether the design is correct

Stimulus ──┬──→ DUT ──→ Actual ──┐
           │                      ├──→ Scoreboard ──→ PASS / FAIL
           └──→ Model ──→ Expected┘

Why This Matters

• Directed tests catch known bugs. Self-checking + constrained-random catches the bugs you didn't think of.

• Regression safety. Change one line of RTL, re-run 500 random seeds, get automatic pass/fail.

• Scales to real designs. Same architecture verifies an ALU or a PCIe controller.

I use Nim to build golden models and stimulus generators because it compiles to C (fast enough for simulation) and catches constraint errors at compile time. But the self-checking architecture works with any language.

Stop printing values and eyeballing them. Build infrastructure that checks for you.

The full methodology — self-checking patterns, constrained-random stimulus, SVA generation, functional coverage, and production regression flows — is what I teach in the NimBench Academy course.

Welcome to the course. Here's how to get the most out of your membership.

Your Learning Path

1. Start the course — Lessons are sequential. Begin with Chapter 1 and work through in order.

2. Set up your environment — You'll need Icarus Verilog (free) and Nim. Both install in under 5 minutes.

3. Complete every exercise — Each lesson ends with a hands-on exercise. These build on each other and culminate in the capstone project.

4. Use the community chat — Ask questions, share your progress, and get feedback from fellow verification engineers.

Resources

• Icarus Verilog: brew install icarus-verilog (macOS) or apt install iverilog (Ubuntu)

• Nim: curl https://nim-lang.org/choosenim/init.sh -sSf | sh

• Capstone RTL files will be posted here when you reach Chapter 6

Pace Recommendation

The course is designed for 2-3 lessons per week. You'll complete the full program and capstone in about 6 weeks. Faster is fine — but give yourself time to implement each exercise.

Let's build testbenches that actually work. See you in Lesson 1.

Test