{"type":"doc","content":[{"type":"heading","attrs":{"level":2},"content":[{"type":"text","text":"Welcome, future FSM architect!"}]},{"type":"paragraph","content":[{"type":"text","text":"You've just joined "},{"type":"text","marks":[{"type":"bold"}],"text":"StateLogic Pro"},{"type":"text","text":" — the only course that bridges modern Nuxt 3 SSR coaching with hardcore VHDL finite state machine design. Here's how to get the most out of your membership:"}]},{"type":"orderedList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","marks":[{"type":"bold"}],"text":"Start the course sequentially."},{"type":"text","text":" Each chapter builds on the last — from combinational logic refreshers all the way to a full UART receiver capstone project."}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","marks":[{"type":"bold"}],"text":"Use the Community Chat."},{"type":"text","text":" Post questions, share your VHDL code snippets, and help fellow engineers debug their state machines."}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","marks":[{"type":"bold"}],"text":"Check Updates & Resources regularly."},{"type":"text","text":" I'll drop supplemental testbench templates, encoding cheat sheets, and synthesis tips here."}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","marks":[{"type":"bold"}],"text":"Complete the capstone."},{"type":"text","text":" Building the UART Receiver FSM end-to-end is what separates textbook knowledge from real FPGA skill."}]}]}]},{"type":"paragraph","content":[{"type":"text","text":"Your 1-day free trial gives you full access — dive in immediately. Let's turn state diagrams into synthesized hardware. 🚀"}]}]}

{"type":"doc","content":[{"type":"paragraph","content":[{"type":"text","text":"If you're writing VHDL and your state machines still feel like guesswork — you're leaving performance, reliability, and career growth on the table."}]},{"type":"paragraph","content":[{"type":"text","text":"FSMs are the backbone of every serious digital design: UART controllers, SPI interfaces, protocol arbiters, video pipelines. Yet most engineers never learn the "},{"type":"text","marks":[{"type":"italic"}],"text":"why"},{"type":"text","text":" behind encoding choices, safe-state strategies, or how to write testbenches that actually catch bugs before silicon."}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"text","text":"What you'll learn inside StateLogic Pro:"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","text":"Moore vs. Mealy architectures — when each one wins and why"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","text":"Binary, one-hot, and Gray encoding trade-offs for real FPGAs"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","text":"Self-checking testbenches and waveform debugging workflows"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"text","text":"A full capstone: design, verify, and synthesize a UART Receiver FSM"}]}]}]},{"type":"paragraph","content":[{"type":"text","text":"This isn't another theory dump. It's 6 chapters of hands-on, sequential lessons built for engineers who want to "},{"type":"text","marks":[{"type":"bold"}],"text":"ship hardware that works"},{"type":"text","text":". Start your 1-day free trial and see for yourself."}]}]}